Power transistors (semiconductor devices) are used as switching elements for power amplification circuits, power supply circuits and the like. This kind of power transistors has a construction in which a plurality of transistor elements are electrically connected in parallel. Each of the transistor elements is constructed as, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) of trench gate structure. A method of fabricating a power transistor having a MISFET of trench gate structure will be described below.
First, an n−-type semiconductor layer is formed over a major surface of an n+-type semiconductor substrate made of single-crystal silicon by an epitaxial growth method. These n+-type semiconductor substrate and n−-type semiconductor layer are used as a drain region. Then, p-type impurities are introduced into the entire major surface of the n−-type semiconductor layer by ion implantation to form a p-type semiconductor region to be used as a channel forming region. Then, n-type impurities are selectively introduced into the major surface of the p-type semiconductor region by ion implantation to form an n+-type semiconductor region which serves as a source region.
Then, after, for example, a silicon oxide film has been formed over the major surface of the n−-type semiconductor layer, patterning is applied to the silicon oxide film to form a mask having an opening above a trench forming region of the n−-type semiconductor layer. Then a trench is formed from the major surface of the n−-type semiconductor layer in the depth direction thereof by using the mask as an etching mask. The formation of the trench is performed by an anisotropic dry etching method.
Then, wet etching is applied to allow the mask to recede from the top edge portion of the trench (the portion of intersection of the side surface of the trench and the major surface of the n−-type semiconductor layer). Then, isotropic dry etching is applied to form the top edge portion and the bottom edge portion (the portion of intersection of the side surface of the trench and the bottom surface thereof) of the trench into gently-sloping shapes, respectively. Then, the mask is removed.
Then, thermal oxidation is applied to form a sacrifice thermal oxide film over the internal surface of the trench, and then the sacrifice thermal oxide film is removed. The formation and the removal of the sacrifice thermal oxide film are performed for the purpose of removing defects, strain, contamination and the like which are produced when the trench is formed.
Then, thermal oxidation is applied to form a gate insulating film comprising a thermal oxide film over the internal surface of the trench. Then, a polycrystalline silicon film is formed over the entire major surface of the n−-type semiconductor layer, inclusive of the inside of the trench, by a chemical vapor deposition method. Impurities for decreasing the resistance value of the polycrystalline silicon film are introduced into the polycrystalline silicon film during or after the deposition thereof.
Then, etchback is applied to flatten the surface of the polycrystalline silicon film. Then, etching is selectively applied to the polycrystalline silicon film to form a gate electrode in the trench and to form a gate lead-out electrode integrated with the gate electrode, over the peripheral region of the major surface of the n−-type semiconductor layer. In this step, a MISFET is formed which has a trench gate structure in which the gate electrode is formed in the trench of the n−-type semiconductor layer, with the gate insulating film interposed therebetween
Then, an interlayer insulating film is formed over the entire major surface of the n−-type semiconductor layer, inclusive of the top surface of the gate electrode, and then a contact hole is formed in the interlayer insulation film. After that, a source interconnection and a gate interconnection are formed, and then a final passivation film is formed. After that, a bonding opening is formed in the final passivation film, and then a drain electrode is formed on the back of the n+-type semiconductor substrate, whereby a power transistor having such a MISFET of trench gate structure is almost finished.
The MISFET having the trench gate structure constructed in this manner can be reduced in its occupation area compared to a MISFET in which its gate electrode is formed on the major surface of its semiconductor layer, with a gate insulating film interposed therebetween. Accordingly, the size and on resistance of the power transistor can be reduced.
Incidentally, a power transistor having a MISFET of trench gate structure is described in, for example, EP 666,590.